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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. a 04/30/03 is62WV5128ALL is62wv5128bll issi ? copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 512k x 8 low voltage, ultra low power cmos static ram features ? high-speed access time: 55ns, 70ns cmos low power operation 36 mw (typical) operating 9 w (typical) cmos standby ttl compatible interface levels single power supply 1.65v ? 2.2v v dd (is62WV5128ALL) 2.5v ? 3.6v v dd (is62wv5128bll) fully static operation: no clock or refresh required three state outputs industrial temperature available description the issi is62WV5128ALL / is62wv5128bll are high- speed, 4m bit static rams organized as 512k words by 8 bits. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high- performance and low power consumption devices. when cs1 is high (deselected) the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs. the active low write enable (we) controls both writing and reading of the memory. the is62WV5128ALL and is62wv5128bll are packaged in the jedec standard 32-pin tsop (type i), 32-pin stsop (type i), and 32-pin tsop (type ii). functional block diagram april 2003 a0-a18 cs1 oe we 512k x 8 memory array decoder column i/o control circuit gnd v dd i/o data circuit i/o0-i/o7
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 04/30/03 is62WV5128ALL, is62wv5128bll issi ? 32-pin tsop (type i), (package code t) 32-pin stsop (type i) (package code h) 32-pin tsop (type ii) (package code t2) pin descriptions a0-a18 address inputs cs1 chip enable 1 input oe output enable input we write enable input i/o0-i/o7 input/output nc no connection v dd power gnd ground pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 we a18 a15 v dd a17 a16 a14 a12 a7 a6 a5 a4 oe a10 cs1 i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a17 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd a15 a18 we a13 a8 a9 a11 oe a10 cs1 i/o7 i/o6 i/o5 i/o4 i/o3 v dd
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. a 04/30/03 is62WV5128ALL, is62wv5128bll issi ? dc electrical characteristics (over operating range) symbol parameter test conditions v dd min. max. unit v oh output high voltage i oh = -0.1 ma 1.65-2.2v 1.4 ? v i oh = -1 ma 2.5-3.6v 2.2 ? v v ol output low voltage i ol = 0.1 ma 1.65-2.2v ? 0.2 v i ol = 2.1 ma 2.5-3.6v ? 0.4 v v ih input high voltage 1.65-2.2v 1.4 v dd + 0.2 v 2.5-3.6v 2.2 v dd + 0.3 v v il (1) input low voltage 1.65-2.2v ?0.2 0.4 v 2.5-3.6v ?0.2 0.6 v i li input leakage gnd v in v dd ?1 1 a i lo output leakage gnd v out v dd , outputs disabled ?1 1 a notes: 1. v il (min.) = ?1.0v for pulse width less than 10 ns. absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.2 to v dd +0.3 v v dd v dd related to gnd ?0.2 to v dd +0.3 v t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating range (v dd ) range ambient temperature is62WV5128ALL is62wv5128bll commercial 0c to +70c 1.65v - 2.2v 2.5v - 3.6v industrial ?40c to +85c 1.65v - 2.2v 2.5v - 3.6v
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 04/30/03 is62WV5128ALL, is62wv5128bll issi ? ac test loads figure 1 figure 2 capacitance (1) symbol parameter cond itions max. unit c in input capacitance v in = 0v 8 pf c out input/output capacitance v out = 0v 10 pf note: 1. tested initially and after any design or process changes that may affect these parameters. ac test conditions parameter is62WV5128ALL is62wv5128bll (unit) (unit) input pulse level 0.4v to v dd -0.2v 0.4v to v dd -0.3v input rise and fall times 5 ns 5ns input and output timing v ref v ref and reference level output load see figures 1 and 2 see figures 1 and 2 is62WV5128ALL is62wv5128bll 1.65 - 2.2v 2.5v - 3.6v r1( ?) 3070 3070 r2( ?) 3150 3150 v ref 0.9v 1.5v v tm 1.8v 2.8v r1 30 pf including jig and scope r2 output vtm r1 5 pf including jig and scope r2 output vtm
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. a 04/30/03 is62WV5128ALL, is62wv5128bll issi ? power supply characteristics (1) (over operating range) 62WV5128ALL (1.65v - 2.2v) symbol parameter test conditions max. unit 70 ns i cc v dd dynamic operating v dd = max., com. 25 ma supply current i out = 0 ma, f = f max ind. 30 i cc 1 operating supply v dd = max., cs1 = 0.2v com. 10 ma current we = v dd -0.2v ind. 10 f=1 mhz i sb 1 ttl standby current v dd = max., com. 0.35 ma (ttl inputs) v in = v ih or v il ind. 0.35 cs1 = v ih , f = 1 mh z i sb 2 cmos standby v dd = max., com. 15 a current (cmos inputs) cs1 v dd ? 0.2v, ind. 15 v in v dd ? 0.2v, or v in 0.2v, f = 0 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. power supply characteristics (1) (over operating range) 62wv5128bll (2.5v - 3.6v) symbol parameter test conditions max. max. unit 55 ns 70 ns i cc v dd dynamic operating v dd = max., com. 40 35 ma supply current i out = 0 ma, f = f max ind. 45 40 i cc 1 operating supply v dd = max., cs1 = 0.2v com. 15 15 ma current we = v dd -0.2v ind. 15 15 f=1 mhz i sb 1 ttl standby current v dd = max., com. 0.35 0.35 ma (ttl inputs) v in = v ih or v il ind. 0.35 0.35 cs1 = v ih , f = 1 mh z i sb 2 cmos standby v dd = max., com. 15 15 a current (cmos inputs) cs1 v dd ? 0.2v, ind. 15 15 v in v dd ? 0.2v, or v in 0.2v, f = 0 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 04/30/03 is62WV5128ALL, is62wv5128bll issi ? ac waveforms read cycle no. 1 (1,2) (address controlled) ( cs1 = oe = v il , we = v ih ) data valid previous data valid t aa t oha t oha t rc d out address read cycle switching characteristics (1) (over operating range) 55 ns 70 ns symbol parameter min. max. min. max. unit t rc read cycle time 55 ? 70 ? ns t aa address access time ? 55 ? 70 ns t oha output hold time 10 ? 10 ? ns t acs1 cs1 access time ? 55 ? 70 ns t doe oe access time ? 25 ? 35 ns t hzoe (2) oe to high-z output ? 20 ? 25 ns t lzoe (2) oe to low-z output 5 ? 5 ? ns t hzcs1 cs1 to high-z output 0 20 0 25 ns t lzcs1 cs1 to low-z output 10 ? 10 ? ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0 .4 to v dd -0.2v/v dd -0.3v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. a 04/30/03 is62WV5128ALL, is62wv5128bll issi ? ac waveforms read cycle no. 2 (1,3) ( cs1 , oe controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , cs1 = v il . we =v ih . 3. address is valid prior to or coincident with cs1 low transition. t rc t oha t aa t doe t lzoe t acs1 t lzcs1 t hzoe high-z data valid t hzcs address oe cs1 dout
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 04/30/03 is62WV5128ALL, is62wv5128bll issi ? write cycle switching characteristics (1,2) (over operating range) 55 ns 70 ns symbol parameter min. max. min. max. unit t wc write cycle time 55 ? 70 ? ns t scs1 cs1 to write end 45 ? 60 ? ns t aw address setup time to write end 45 ? 60 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup time 0 ? 0 ? ns t pwe we pulse width 40 ? 50 ? ns t sd data setup to write end 25 ? 30 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe (3) we low to high-z output ? 20 ? 20 ns t lzwe (3) we high to low-z output 5 ? 5 ? ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0 .4v to v dd -0.2v/v dd -0.3v and output loading specified in figure 1. 2. the internal write time is defined by the overlap of cs1 low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that termi nates the write. 3. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. ac waveforms write cycle no. 1 ( cs1 controlled, oe = high or low ) data-in valid data undefined t wc t scs1 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address cs1 we dout din
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. a 04/30/03 is62WV5128ALL, is62wv5128bll issi ? write cycle no. 2 ( we controlled: oe is high during write cycle) write cycle no. 3 ( we controlled: oe is low during write cycle) data-in valid data undefined t wc t scs1 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 we dout din data-in valid data undefined t wc t scs1 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 we dout din
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 04/30/03 is62WV5128ALL, is62wv5128bll issi ? data retention switching characteristics symbol parameter test condition min. max. unit v dr v dd for data retention see data retention waveform 1.2 3.6 v i dr data retention current v dd = 1.2v, cs1 v dd ? 0.2v ? 15 a t sdr data retention setup time see data retention waveform 0 ? ns t rdr recovery time see data retention waveform t rc ?ns data retention waveform ( cs1 cs1 cs1 cs1 cs1 controlled) v dd cs1 v dd - 0.2v t sdr t rdr v dr cs1 gnd data retention mode
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. a 04/30/03 is62WV5128ALL, is62wv5128bll issi ? ordering information is62WV5128ALL (1.65v - 2.2v) commercial range: 0c to +70c speed (ns) order part no. package 70 is62WV5128ALL-70t tsop, type i 70 is62WV5128ALL-70t2 tsop, type ii 70 is62WV5128ALL-70h stsop, type i industrial range: ?40c to +85c speed (ns) order part no. package 70 is62WV5128ALL-70ti tsop, type i 70 is62WV5128ALL-70t2i tsop, type ii 70 is62WV5128ALL-70hi stsop, type i ordering information is62wv5128bll (2.5v - 3.6v) commercial range: 0c to +70c speed (ns) order part no. package 55 is62wv5128bll-55t2 tsop, type ii 55 is62wv5128bll-55h stsop, type i 70 is62wv5128bll-70t tsop, type i 70 is62wv5128bll-70t2 tsop, type ii 70 is62wv5128bll-70h stsop, type i industrial range: ?40c to +85c speed (ns) order part no. package 55 is62wv5128bll-55ti tsop, type i 55 is62wv5128bll-55t2i tsop, type ii 55 is62wv5128bll-55hi stsop, type i 70 is62wv5128bll-70ti tsop, type i 70 is62wv5128bll-70hi stsop, type i
integrated silicon solution, inc. packaging information issi ? plastic stsop - 32 pins package code: h (type i) notes: 1. controlling dimension: millimeters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d1 and e do not include mold flash protru- sions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic stsop (h - type i) millimeters inches symbol min max min max ref. std. n 32 a ? 1.25 ? 0.049 a1 0.05 ? 0.002 ? a2 0.95 1.05 0.037 0.041 b 0.17 0.23 0.007 0.009 c 0.14 0.16 0.0055 0.0063 d 13.20 13.60 0.520 0.535 d1 11.70 11.90 0.461 0.469 e 7.90 8.10 0.311 0.319 e 0.50 bsc 0.020 bsc l 0.30 0.70 0.012 0.028 s 0.28 typ. 0.011 typ. 0 5 0 5 pk13197h32 rev. b 04/21/03 d1 seating plane c d 1 n e s b a1 a a2 e l
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. e 02/20/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. plastic tsop package code: t (type ii) d seating plane b e c 1 n/2 n/2+1 n e1 a1 a e l zd notes: 1. controlling dimension: millimieters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic tsop (t - type ii) millimeters inches millimeters inches millimeters inches symbol min max min max min max min max min max min max ref. std. no. leads (n) 32 44 50 a ? 1.20 ? 0.047 ? 1.20 ? 0.047 ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018 c 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 d 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830 e1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 e 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471 e 1.27 bsc 0.050 bsc 0.80 bsc 0.032 bsc 0.80 bsc 0.031 bsc l 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024 zd 0.95 ref. 0.037 ref. 0.81 ref. 0.032 ref. 0.88 ref. 0.035 ref 0 5 0 5 0 5 0 5 0 5 0 5
integrated silicon solution, inc. 1 issi packaging information plastic tsop - 32 pins package code: t (type i) d seating plane b e c 1 n e a1 a s h l a notes: 1. controlling dimension: millimeters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic tsop (ttype i) millimeters inches symbol min max min max ref. std. no. leads 32 a 1.20 0.047 a1 0.05 0.25 0.002 0.010 b 0.17 0.23 0.007 0.009 c 0.12 0.17 0.006 0.014 d 7.90 8.10 0.308 0.316 e 18.30 18.50 0.714 0.722 h 19.80 20.20 0.772 0.788 e 0.50 bsc 0.020 bsc l 0.40 0.60 0.016 0.024 a 0 8 0 8 pk13197t32 rev. b 01/31/97

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